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Bridging the Gap

Training Courses

VHDL for Synthesis

Course id: 0021


Field Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture.

This course introduces the complete FPGA development flow and environment with VHDL. The emphasis here is on the subset of VHDL that is synthesizable -- i.e. capable of producing hardware -- rather than the entire HDL. Proper, generic hardware description style and implementation techniques are introduced throughout the course.

Course highlight Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera's Quartus II development software and Mentor Graphic's ModelSim-Altera simulator.

This course is similar to the Verilog for Synthesis course.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
  • Familiarise with Altera's Quartus II and Graphics's ModelSim for design entry, analysis and simulation
  • Know the fundamentals of VHDL, with particular emphasis on synthesizable constructs (i.e. able to generate hardware)
  • Describe combinational and sequential circuits in a structural and behavioral manner
  • Develop digital systems in a hierarchical and modular nature to aid testing, debugging and hardware reuse
  • Learn and use VHDL constructs for simulation and verification with testbenches
  • Describe the operation of sequential circuits in the Register Transfer Level (RTL) notation
  • Describe control flow with Algorithmic State Machines (ASM) and implement them in VHDL

Who should attend

This course is particularly suited for engineers involved in digital design and testing who are new to the HDL flow.


Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. This course is the recommended prerequisite for the "Advanced Synthesis with VHDL" course.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with hands-on practical for maximum understanding.

Course duration

4 days.

Course structure

  • Introduction
    • HDL design flow
    • History of VHDL
    • Structural HDL
    • Behavioral HDL description
    • Hands-on Practical 1: Introduction to Quartus II
  • Basic VHDL 1
    • Language constructs
    • Data types and representation
    • Component instantiation
    • Concurrent statements
    • Operators
    • Multiplexers
    • Hands-on Practical 2: Combinational Logic
  • Basic VHDL 2
    • Concatenation
    • Repetition
    • Aggregates and array slices
    • Enumeration
    • RAMs and ROMs
    • Hands-on Practical 3: Seven Segment Decoder
  • Sequential Design
    • Register basics
    • Sequential statements
    • Blocking assignments
    • Registers, latches and counters
    • Hands-on Practical 4: Up/Down Counter
  • Modularisation
    • Hierarchical design
    • Parameterization
    • Generation
    • Hands-on Practical 5: Real-time Clock
  • State Machine
    • Registers transfer operations
    • Algorithmic State Machine
    • Hands-on Practical 6: Serial Transceiver (Transmission)
  • Testbenches
    • Introduction
    • Testbench methods
    • Hands-on Practical 7: ModelSim-Altera Simulations
  • Hands-on Practical 8: Serial Transceiver (Reception)


Dr Royan Ong

Course Schedule





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