Training Courses

Developing Simulations and Testbenches in VHDL

Course id: 0048

Synopsis

Field Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture.

This course introduces the design and implementation of testbenches for simulating and verifying digital systems.

Course highlight
Participants will have practical design experience using industry-standard logic simulators (e.g. Synopsys VCS-MX or Mentor Graphics ModelSim).

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:

Simulate digital circuits with Synopsys' VCS-MX or Mentor Graphics ModelSim
Learn and use VHDL constructs for simulation and verification
Design tester components such as stimuli / test vector generators, transaction monitors, response checkers, and scoreboards
Design testbench components with simple assertions, file I/O, and constrained random verification (CRV)
Have an overview of advanced techniques such as transaction-level modelling (TLM), bus functional modelling (BFM), temporal assertions-based verification (ABV), and functional coverage

Who should attend

This course is particularly suited for engineers involved in HDL-flow digital design simulation, verification and testing.

Prerequisite

Participants should have a degree in electronics (and related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesizable digital systems or simulation testbenches.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course duration

3 days.

Course structure

Introduction
- IC/FPGA design and verification flow
- The Design Under Verification (DUV)
- Overview of testbench components
Stimuli vector generator design
- Concept of test vector generation, types of stimuli (directed, pseudorandom)
- Unconstrained vs. constrained randomisation
- Unconstrained randomisation of stimuli
- Hands-on Practical 1: Unconstrained random stimuli vector generator design and simulation
- Constrained random verification (CRV)
- Hands-on Practical 2: Constrained random stimuli vector generator design and simulation
- File I/O (input only)
- Hands-on Practical 3: Reading stimuli from a file
Transaction monitor design
- Concept of transaction monitoring
- Simple (non-temporal) assertions-based verification (ABV)
- Hands-on Practical 4:Transaction monitor design using non-temporal assertions
Response checker design
- Concept of response checking
- Scoreboards
- Hands-on Practical 5: Response checker design using scoreboards logged to simulator's console
- File I/O (output only)
- Hands-on Practical 6: Response checker design using scoreboards logged to a file
Overview of advanced testbench techniques
- Temporal assertions-based verification (ABV) with Property Specification Language (PSL)
- Functional coverage
- Transaction-level modelling (TLM) and bus functional modelling (BFM)

Course Schedule

Consultancy

Technical Consultancy

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  Kuala Lumpur, Malaysia

Tel: +603 03 5889 5889

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