Consultancy and Total Solutions Training Provider for Embedded Systems, Electronics and Electrical Engineering, Programming, Computing, Operations, ISO9000, ISO14000 and Management.

Bridging the Gap

Training Courses

Pipelined RISC Processor Architecture

Course id: 0060


The digital age heralds the need for vast data processing and number crunching capabilities to satisfy our insatiable needs. Applications such as video compression/ decompression, voice recognition and 3D graphics typically required electronic devices to incorporate some form of hardware acceleration to produce the required processing throughput.

This course covers the essential concepts of pipelining, caveats and pitfalls associated with dependencies, and mitigation techniques to reduce the impact of dependencies.

Course highlight
Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera's Quartus II development software. They will, at the end of the course, complete a pipelined MIPS-like processor.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
  • Understand the pipelining paradigm and related issues such as structural, control and data hazards
  • Implement pipelining to maximize computation throughput
  • Reduce or eliminate data dependencies with forwarding units
  • Prevent control hazards with hazard detection units

Who should attend

This course is particularly suited for engineers involved in the design of processors or processing cores to achieve high processing speeds.


Participants should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems. They must have the knowledge of developing synthesizable hardware in Verilog, and have an understanding of algorithmic state machines (ASM).

Course methodology

This course is presented in a workshop style with lectures interlaced with demonstrations and hands-on practicals for maximum understanding.

Course duration

3 days.

Course structure

  • Introduction
    • Overview of pipelining
    • Advantages of pipelining
    • Caveats and pitfalls of pipelining
  • Implementing Pipelining
    • Pipelined Datapath
    • Pipeline registers
    • Hands-on practical 1: Pipelining a Processor
    • Controlling the pipeline
    • Hands-on practical 2: Pipelined Control Unit
  • Hazards, Dependencies and Mitigation
    • Structural Hazards
    • Data Hazards
    • Forwarding Unit
    • Hands-on practical 3: Implementing the Forwarding Unit
    • Hazard Detection Unit
    • Control Hazards
    • Early Branch Decision
    • Hands-on practical 4: Mitigating Control Hazards


Dr Royan Ong

Course Schedule





News on ProvenPac

  ProvenPac Sdn. Bhd.
  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

  Tel: +603 03 5889 5889

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