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Bridging the Gap

Training Courses

Register Transfers and Sequencing in Verilog

Course id: 0045


Field Programmable Gate Arrays have allowed engineers to develop complex, sophisticated and extremely fast digital systems. Due to their versatility, they are also by far the most feasible option for prototyping. The complexity of digital systems however, meant it is more than necessary to develop such systems in hardware description languages (HDL) rather than schematic capture.

This course concentrates on the register transfer level (RTL) of abstraction for the signal pathways of digital systems, and introduces the algorithmic state machine (ASM) design methodology to control the pathways.

Course highlight
Participants will have practical design experience using the Altera DE2 FPGA development board, together with the use of Altera’s Quartus II development software.

Participants would develop a simple pipelined MIPS processor using the modules developed during the Verilog Design for Synthesis course. Alternatively, participants could develop a serial communication module akin to SPI, as part of the hands-on practical.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
  • Describe the operation of sequential circuits in the Register Transfer Level (RTL) notation
  • Partition digital systems along the lines of the datapath and control unit
  • Describe control flow with Algorithmic State Machines (ASM)
  • Efficiently and easily implement ASMs in Verilog
  • Understand the concepts of microprocessors and implementing them

Who should attend

This course is particularly suited for engineers involved in designs that require state machine control, which is typical of most digital systems.


Participants must have completed the Verilog for Synthesis course. They should have a diploma/degree in electronics (and related) engineering with an understanding of digital systems.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course duration

3 days.

Course structure

  • Register Transfer Level
    • Overview
    • RTL notation
  • Introduction to MIPS
    • The MIPS architecture
    • Instruction Set Architecture (subset)
    • Instruction cycle
    • Memory access
    • Branching
    • Hands-on Practical 1: Operations in RTL
  • Partitioning
    • Design partitioning of datapath and control
    • Hands-on Practical 2: Processor Control Unit
  • Algorithmic State Machine
    • Overview of ASM
    • Hands-on Practical 3: ASM for a Non-pipelined MIPS
    • ASMs to Verilog
    • Hands-on Practical 4: Implementation of a Non-pipelined MIPS
  • Pipelined MIPS
    • Overview of pipelining
    • Pipelined MIPS
    • Hands-on Practical 5: Implementation of a Pipelined MIPS


Dr Royan Ong

Course Schedule





News on ProvenPac

  ProvenPac Sdn. Bhd.
  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

  Tel: +603 03 5889 5889

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