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Bridging the Gap

Training Courses

Developing AMBA AXI-compliant Modules for System-On-Chip Designs

Course id: 0051


As systems-on-chips (SoC) integrate increasingly more features on a chip, the sheer complexity demands a paradigm shift in design. With multiple inter-module routing groups within an SoC, it is no longer feasible for bus interfaces to be designed using conventional low-level signalling methodologies.

This course introduce the concept of transaction-level modelling (TLM) and bus functional modelling (BFM), which are methods to encapsulate low-level signalling into high-level transactions. TLMs/BFMs simplify testbench and system-level designs by separating the low-level bus models (BFMs) from the higher-level transactor abstractions (TLMs), simplifying the management making designs easier to manage and maintain. These concepts are very important for testbench simulations as well as synthesisable SoC bus interface designs.

Participants will have an in-depth understanding of TLMs and BFMs, and will design transactors and bus functional models for the AMBA AXI4-Stream protocol used in numerous real-world applications. We demonstrate how modules could easily communicate with one another via AXI4-Stream using TLM and BFM techniques.

Course highlight
Participants will have practical design experience using industry-standard logic simulators (Mentor Graphics QuestaSim or Synopsys VCS-MX), logic synthesis tools (Synopsys Design Compiler or Xilinx Vivado), and Xilinx Zynq FPGAs.

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
  • Develop and implement TLM and BFM techniques in bus protocol designs
  • Design and simulate AXI4-Stream transactors and BFMs
  • Synthesize and verify AXI4-Stream transactors and BFMs

Who should attend

This course is particularly suited for engineers involved in ARM-based system-on-chip designs, verification and testing.


Participants must have a degree in electronics (and related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog for developing synthesizable digital systems or simulation testbenches.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course duration

3 days.

Course structure

  • Introduction
    • Overview of transaction-level modelling (TLM)
    • Overview of bus functional modelling (BFM)
    • Introduction to the AXI4-Stream protocol
  • Transactor design
    • Concept of transactions
    • Concept of TLM and its applications
    • Typical example of a transaction-level model (transactor)
    • Hands-on Practical 1: Designing AXI4-Stream master transactors
  • Bus functional model design
    • Concept of BFM
    • Hands-on Practical 2: BFM design of the AXI4-Stream master
  • Transactor and BFM simulation
    • Setting up Mentor Graphics QuestaSim/Synopsys VCS-MX for simulations
    • TLM simulation of the simulation of the AXI4-Stream Master
    • BFM model simulation
    • Hands-on Practical 3: Simulating AXI4-Stream Master TLM/BFM models
  • Transactor and BFM synthesis
    • Setting up the Synopsys Design Compiler synthesis tool
    • Setting up Vivado/Quartus synthesis, auto-placement-and-routing (APR), and design assembly tools
    • Sythesizing AXI4-Stream Master TLM and BFM models
    • Hands-on Practical 4: Integrating AXI4-Stream Master with the ARM Cortex-A9 processor
  • Transactor and BFM verification
    • Hardware verification flow for post-PAR
    • Setting up Xilinx ChipScope Pro
    • Hands-on Practical 5: Verification of AXI4-Stream TLM/BFM design
  • Functional verification
    • Setting up the programming environment
    • Developing C programs for functional testing
    • Hands-on Practical 6: Functional verification of AXI4-Stream TLM/BFM

Course Schedule





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  ProvenPac Sdn. Bhd.
  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

  Tel: +603 03 5889 5889

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