Consultancy and Total Solutions Training Provider for Embedded Systems, Electronics and Electrical Engineering, Programming, Computing, Operations, ISO9000, ISO14000 and Management.

Bridging the Gap

Training Courses

Transaction-level Modelling and Bus Functional Modelling

Course id: 0050


As systems-on-chips (SoC) integrate increasingly more features on a chip, the sheer complexity demands a paradigm shift in design. With multiple inter-module routing groups within an SoC, it is no longer feasible for bus interfaces to be designed using conventional low-level signalling methodologies.

We introduce the concept of transaction-level modelling (TLM) and bus functional modelling (BFM) in this course, which are methods to encapsulate low-level signalling into high-level transactions. TLM/BFM simplify testbench and system-level designs by separating the low-level bus models from the higher-level transactor abstractions, making your testbenches/SoC designs easier to manage and maintain. These concepts are very important for testbench simulations as well as synthesisable SoC bus interface designs.

Participants will have an in-depth understanding of TLMs and BFMs, and will design transactors and bus functional models for a simple FIFO application, commonly found in numerous real-world applications. We demonstrate how modules could easily communicate with one another via a bus interface designed using TLM and BFM techniques. Communicating between two individual testbench/SoC components is as simple as making a procedure-call statement.

Course highlight
Participants will have practical design experience using industry-standard logic simulators, logic synthesis tools and development platforms (Xilinx Zynq/Altera Cyclone V)

What you will learn

This course concentrates on the theoretical and practical knowledge to allow participants to achieve the following learning outcomes. Upon completing the course, participants would be able to:
  • Develop and implement TLM and BFM techniques in bus protocol designs
  • Design and simulate transactors and BFMs
  • Synthesize and verify transactors and BFMs

Who should attend

This course is particularly suited for engineers involved with system-on-chip (SoC) design, verification and testing.


Participants should have a degree in electronics (and related) engineering with an understanding of digital systems. They must be familiar with VHDL/Verilog/SystemVerilog for developing synthesizable digital systems and testbenches.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with demonstrations and hands-on practical for maximum understanding.

Course duration

3 days.

Course structure

  • Introduction
    • Overview of transaction-level modelling (TLM)
    • Overview of bus functional modelling (BFM)
  • Transactor design
    • Concept of transactions
    • Concept of TLM and its applications
    • Review of VHDL procedures
    • Typical example of a transaction-level model (transactor)
    • Hands-on Practical: Designing a FIFO master transactor
  • Bus functional model design
    • Concept of BFM
    • Hands-on Practical: BFM design of the FIFO master
  • Transactor and BFM simulation
    • Setting up Mentor Graphics QuestaSim/Synopsys VCS-MX for simulations
    • Hands-on Practical: Simulating the FIFO Master TLM/BFM models
  • Transactor and BFM synthesis
    • Setting up the Synopsys Design Compiler synthesis tool
    • Setting up Vivado/Quartus synthesis, auto-placement-and-routing (APR), and design assembly tools
    • Hands-on Practical: Synthesising the FIFO Master TLM and BFM models
  • Transactor and BFM verification
    • Hardware verification flow for post-PAR
    • Setting up Xilinx ChipScope Pro
    • Hands-on Practical: Verification of the FIFO TLM/BFM design
  • Synthesis and Layout Optimisation Techniques
    • Optimising for area and power: RTL optimisation techniques
    • Optimising for speed: static timing analysis (STA), floorplanning and manual placement techniques for high-performance design
    • Hands-on Practical: Optimising the design for area, power, and speed

Course Schedule





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  ProvenPac Sdn. Bhd.
  C-4-3 Gembira Park,
  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

  Tel: +603 03 5889 5889

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