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Bridging the Gap

Training Courses

Verilog: Small and Fast

Course id: 0028


A hardware description language (HDL) is a language for formal description and design of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.

In traditional chip design, there is the classic trade-off between clock speed and chip area size. As HDL designers are focused on functionality, there may be a tendency to write bad HDL code and depend on the synthesis tool to constrain the area and speed of the final hardware.

There is a better way however, that is to write optimal HDL that will result in hardware that is both small and fast – having your cake and eating it too!

This course uses Verilog, though it can be tailored for VHDL.

Course highlight
Participants will have practical experiences analysing, designing, writing, verifying cores in HDL. Participants will gain an appreciation for how to write better HDL to encourage the hardware to become small and fast.

Xilinx ISE and other tools will be used for this purpose.

What you will learn

This course comprises of the following main topics:
  • Reviewing the speed-area trade-off.
  • Small and fast asynchronous logic.
  • Small and fast synchronous logic.
  • Small and fast functional blocks.

Who should attend

This course is particularly suited for engineers responsible for designing and implementing digital chip-design systems.


Participants must be familiar with synthesisable Verilog at the RTL level.

Course methodology

This course is presented in a workshop style with example-led lectures interlaced with hands-on practical for maximum understanding.

Course duration

3 days.

Course structure

  • Review
    • Review of RTL level Verilog code.
    • Review of synthesisable Verilog.
  • Introduction
    • The tradeoff between speed and area.
    • Relation of speed-area to power.
    • Lowering the speed-area curve.
  • Target Technology
    • Affects of target-technology on speed-area.
    • Comparison of target technologies.
    • Targeting specific technologies.
  • Asynchronous Logic
    • Advantages and Disadvantages of Positive and Negative logic.
    • Handling multiple input logic.
    • Dealing with multiple logic levels.
    • Effects of badly written Verilog.
  • Synchronous Logic
    • Advantages and Disadvantages of Positive and Negative logic.
    • Developing fast, compact Finite State Machines.
    • Implementing non-binary Counters.
    • Effects of badly written Verilog.
  • Other Functions
    • Routing and handling Reset.
    • Implementing Memory.
    • Reducing Arithmetic complexity.
    • Designing proper Shift.
  • Discussion & Conclusion

Course Schedule





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  Jalan Riang, 58200
  Kuala Lumpur, Malaysia

  Tel: +603 03 5889 5889

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