Training Courses

Coding Verilog for Portability

Course id: 0029

Synopsis

Due to the nature of the back-end technology, most HDL code is targeted at specific technologies, and even specific technology libraries. This reduces design portability to the point that changes in target technology normally require significant rework that increases NRE cost.

There is a better way however, that is to write portable HDL that will result in hardware that can be used for multiple target technologies.

This course uses Verilog, though it can be tailored for VHDL.

Course highlight
Participants will have practical experiences analysing, designing, writing, verifying cores in HDL. Participants will gain an appreciation for how to write better HDL to encourage the hardware to be target technology agnostic.

Xilinx ISE and Altera Quartus and other tools will be used for this purpose.

What you will learn

• Reviewing target technology.
• Understanding target technology differences.
• Choosing the right strategies for portability.

Who should attend

Prerequisite

Course methodology

Course duration

Course structure

• Review
  • Review of RTL level Verilog code.
  • Review of synthesisable Verilog.
• Target Technology
  • Why is normal Verilog not agnostic?
  • Affect of target technologies on Verilog code.
  • Overview of ASIC Technologies.
  • Overview of FPGA Technologies.
• Code Level Portability
  • Partitioning code.
  • Parametric/generic code.
  • Using configurable defines.
  • Effects of badly written Verilog.
• Design Level Portability
  • The results of Synthesis Inference.
  • Writing module instantiations for portability.
  • Proper usage of design blocks.
  • Effects of badly written Verilog.
• Discussion & Conclusion

Course Schedule

Consultancy

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  Tel: +603 03 5889 5889

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this course is scheduled.

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arrange in-house training.